1. Field of the Invention
The present invention generally relates to testing of application specific integrated circuits (ASICS) and, more particularly, to the testing of analog cores when included therein.
2. Description of the Prior Art
The high performance and reliability of integrated circuits has led to the development not only of integrated circuits of general applicability such as processors, logic arrays and memories but special purpose circuits, as well. Such special purpose circuits of designs which are not necessarily manufactured in large volume are generically referred to as application-specific integrated circuits (ASICS) and may comprise specially adapted digital logic circuits and analog circuits, referred to hereinafter as cores, as well. It is often advantageous to include digital and analog circuits on the same chip for economy of packaging, short signal propagation time and noise immunity, particularly when the digital circuits are used to exercise control over the analog circuits.
Whether of general or specific applicability, integrated circuits must be tested to assure their functionality as part of the manufacturing process. So-called burn-in may also be required to allow the electrical properties which will be maintained by the integrated circuit once it is placed in service to be ascertained.
Digital logic integrated circuits of general applicability such as processors and memories, of course, represent the majority of integrated circuit devices currently being manufactured. Nevertheless, libraries of circuits and designs (the specific circuit design and specifications sometimes being individually referred to as "books" or "macros") which have been developed for inclusion in ASICs exist and may be included in the design of any integrated circuit. Such special-purpose circuits may be generically referred to as cores or macros.
Apparatus for testing and/or burn-in of integrated circuits is complex and costly, particularly since it must include precision power supplies of relatively high current capacity, high frequency, low-noise signal generators, complex switching arrangements or interface cards to direct power and signals to desired connections (e.g. pins) of the integrated circuit device or module and contact arrays which can make temporary contacts with hundreds or thousands of pins while withstanding potentially hundreds of package insertions without causing damage or wear to the package, chip or structure in an intermediate state of packaging.
Accordingly, designs of such apparatus have generally been directed to burn-in and testing of general purpose integrated circuit designs which only require a few power supplies, at most, when different technologies are used in the chip or module (e.g. so-called BiCMOS including both bipolar and CMOS transistor circuits). Likewise, pin-out patterns of standard chips have adopted certain conventions for the placement of power, input and output pins to reduce switching circuit complexity in testers.
Even in such hybrid circuits, so-called level-shifting circuits are sometimes provided to derive plural necessary voltages from a single supply for operation. Burn-in, which is usually conducted at increased voltage, can often be achieved with relatively simple switching arrangements which may be placed on the chip to adjust voltage ratios relative to an elevated burn-in supply voltage applied to the chip or module.
However, ASICs which include analog cores generally require much different voltages for operation (or burn-in) of analog cores than those required for digital cores. Moreover, different analog voltages may be required in view of the intended function or voltage swing of different analog cores which may be included on the same chip, regardless of the technology by which the analog cores are fabricated. In contrast, the operating voltages and logic levels used in digital circuits can be optimized to the electrical properties of the digital circuits. Therefore, provision for applying an increased number of arbitrary voltages which may be required for ASICs of arbitrary design with a fully generalized test apparatus is not economically feasible.
More specifically, ASICs which include both analog cores and digital macros or circuits require multiple decoupled power supplies for normal operation, on pins that would normally be dedicated to signal inputs or outputs (I/Os). Given that chip packaging and connection pin-out patterns have become somewhat standardized, this implies that commercially available and economically feasible testers generally do not include power supplies which can deliver adequate currents or multiple analog voltage levels and, further, accommodate provision of power to connections on ASICs which would receive only signals on a fully digital integrated circuit.
In view of the expense of switching to accommodate provision of power rather than signals to particular integrated circuit package pins, unique or custom interface boards are generally used even though such interface boards are, themselves, very expensive and subject to wear and damage from handling during connection to each of a number of integrated circuits to be tested. Even when the same interface board may be used for different ASIC designs, the cost overhead of interface boards is significant while use of interface boards does not address the issue of the cost of multiple, decoupled, high-current power supplies.
In summary, there has been no technique or apparatus known in the art which is capable of reducing the high cost of testing and/or burn-in of ASICs. Given that ASICs are, by their nature, a low volume product having significant design, development and production costs which can only be amortized over a limited number of devices, significant additional costs of testing and/or burn-in severely limit the applications in which ASICs can be economically employed.